The use of on-board digital processing to provide real time signal processing is becoming increasingly widespread in satellites for telecommunications, Earth observation, science and navigation applications. Rapid advances in the underlying semiconductor technologies are bringing increasingly ambitious digital processing applications within the realms of feasibility.
A typical digital processing system used in a satellite is shown in FIG. 1. The system takes in a number Nin of analogue signal inputs and generates a number Nout of analogue output signals, managed by a control system with access to ground telecommand and telemetry links. The input signals must be digitized in order to be processed numerically and this involves a stage of analogue signal conditioning or “pre-processing” followed by analogue-to-digital (A/D) conversion. Similarly, generation of each output signal involves a stage of digital-to-analogue (D/A) conversion followed by analogue “post-processing”.
Generation of each output signal in general requires information from any or all of the input signals, which means that the digital signal processing function does not decompose simply into what will be referred to as “horizontal slices” (in the sense of a horizontal pathway through the system diagram, representing a 1:1 mapping between an input and a respective output) or processing chains but must provide cross-connections between all inputs and outputs. Both input and output signals may be continuously active and therefore the digital signal processing must also be capable of operating continuously and in real time at a rate commensurate with the signal bandwidth. Increasing the scale of the system by adding more inputs and outputs increases the processing load proportionately but the amount of cross-connection required may increase more substantially, in some cases in proportion to the product Nin×Nout.
Digital systems for use on board a spacecraft face additional challenges beyond those normally experienced by terrestrial systems, and consequently, the cost of qualification of new technology for space flight can be very high. A first necessity for the digital processor is to survive its journey into orbit, for which it must be enclosed in a suitable mechanical housing to withstand the severe vibration and shock levels experienced during launch. Once in orbit it must operate continuously and reliably for many years without maintenance. Stress relief measures must be implemented at all internal interfaces to ensure that sensitive electronic components and assemblies withstand all the mechanical stresses experienced within the satellite environment. The design must also cater for potentially large amounts of heat dissipated by the processor, which must be efficiently removed from the processor to maintain a safe operating temperature. This has to occur primarily by conduction through the metal housing since the on-board processor operates in a vacuum.
The most common engineering solution is to place the processor in a large metal box comprising a back-plane and a set of daughter cards. The box provides a strong mechanical structure, an interface to the spacecraft's thermal management systems and some shielding against ionizing radiation. The main processing components are located on the daughter cards, with interconnects between these occurring via the backplane. The printed circuit board technology used for both daughter cards and back-plane support high density tracks for interconnect, but the provision of suitably robust connectors and the cross-connection of large quantities of interconnect on the hack-plane are challenging. This cross-connection is particularly important for a digital channelizer and router, for example, whose main function is to provide a very high capacity interconnect with as much flexibility as possible between a large number of input and output ports. This implies a very large number of tracks which must cross each other and this can be difficult to manage within the two-dimensional confines of printed circuit board technology while maintaining signal integrity.
The principal disadvantage of the back-plane solution is that is not fully scalable and therefore not ideally optimised to all mission sizes. Specifically, the box and the back-plane printed circuit board must be re-designed and re-qualified for different mission sizes, or else the largest scale box must be used for all missions, which is inefficient within a severely mass-constrained payload.
For a satellite system such as an on-board digital channelizer, which processes uplink beam signals, separates out the wanted channels from interference, and rearranges and routes just the wanted channels for retransmission on appropriate downlink beams and frequencies, the number of cross-connections which are required is usually high. Accordingly, this can be difficult to achieve using a back-plane solution where all the interconnections must be routed within a printed circuit board. In order to be processed digitally, the radio frequency input signals are first filtered and down-converted in frequency to provide a band-limited signal suitable for analogue-to-digital conversion. Each signal corresponds to a relatively wide frequency band segment from an uplink beam (or antenna feed, in the case of an active receive antenna) and generally contains frequency multiplexes consisting of numerous carriers. Each input, after digitization by an A/D converter, is then divided into multiple narrowband channels by a digital channel demultiplexer. Channels may then be individually processed, typically including at least a gain control function, and routed to their destination downlink beams. Since the number of input and output beams is usually high, this routing function must be distributed across a network of switching components within the digital processor. On the output side, all of the channels destined for the same downlink beam are combined by a channel multiplexer to form a wideband signal which is then digital-to-analogue converted. Post-processing is then typically required to generate a suitable radio frequency signal for downlink transmission.
A further disadvantage of highly integrated processor designs, such as the back-plane solution housed in a single box, is that much of the testing can only be performed after the system has been fully assembled. This is an issue particularly for satellite payload equipment which must undergo rigorous environmental qualification testing in a fully representative mechanical and thermal configuration. Ideally such critical phase of testing should be performed earlier in a development programme, when the impact of rectifying any issues discovered is much lower.
There is therefore a need for an improved scaling technique which enables the high number of inputs, outputs and cross-connections typically required for a digital system such as a channelizer on board a spacecraft and which can support a phased integration and test programme.